Multi-GHz CMOS Serial Signaling Circuits
Major Research Area: Integrated Circuits
Sub Research Area: Analog and RF circuits
Abstract: Much research has been done on the implementation of LC oscillators in standard CMOS processes. In applications such as wireline clock-and-data recovery, and RF down conversion, several clock phases are required. Traditionally, in clock-and-data recovery systems, multiple clock phases are generated by rings of delay stages or with the help of interpolation. In RF applications, poly-phase filtering is used to generate quadrature clock phases. Injection-locked rings of LC oscillators can also be used to generate multiple clock phases. This approach is attractive, since, in principle, coupling of LC oscillator stages can result in lower phase noise. Furthermore, coupling also reduces phase errors caused by component mismatch and other non idealities. We use a novel combination of weak MOS transistor based coupling between stages and capacitive averaging to achieve low phase noise and accurate phase spacing.
The goal of this project is the development of techniques for very fast digital serial signaling. This work is supported by the National Science Foundation and the SRC.
Die photograph of the three 5GHz multi phase oscillator rings implemented in 0.18µm CMOS.
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