Resonant Clocking Using Parasitic Capacitance
Major Research Area: Integrated Circuits Sub Research Area: VLSI and digital circuits Abstract: This project studies the ability of resonant circuits to recycle clock energy and reduce clock power, which accounts for over 50% of the power dissipated in modern microprocessors. A test chip was designed in an IBM 0.13µm SOI process with a resonant clock and standard, buffer-driven clock driving the same clock network. The resonant clock was designed with local clock buffers removed so that clock energy would resonate between on-chip inductors and the capacitance in the wires and gates of the clocked circuits. The clock distribution is a part of the clock generation in this scheme. Measurements of the test chip showed the resonant clock dissipated 35% less power than a standard, buffer driven clock at 146MHz. A second test chip was designed in an IBM 0.13µm bulk process that will study resonant clocks in the 1–2GHz range. Also included on the test chip are studies of the effects of the power grid and data-flow on clock performance and a more robust comparison test to standard buffer-driven clocks. The test chip is due back in early 2005. This project is supported by the IBM Austin Center for Advanced Studies. Resonant clock test chip contains several oscillator configurations, standard buffer-driven clock, and circuits for measuring inductor and capacitor quality factors. Faculty:
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Research at the Solid State Electronics Laboratory (SSEL) |
